The present invention relates to memory systems, and more specifically, to column address strobe write latency (CWL) calibration in a memory system.
Present memory interface architectures allow different timing relationships between the command/address/control/clock interface (referred to herein as “address and control logic”) and the data bus at each dynamic random access memory (DRAM) in a memory system. Contemporary architectures include a wiring topology known as “fly-by.” Although this topology improves signal quality, it comes at the expense of flight time (propagation) delay between the nearest and farthest DRAM in a memory subsystem. The relationship between the address and control logic, and the data bus (skew) may create difficulty for a memory controller to assure specific DRAM timing parameters at each DRAM. The memory controller must calibrate data path delays for each DRAM in the system to assure proper timing relationships to the address and control logic.
One such timing relationship is the edge alignment of a write data strobe (DQS) to the memory clock as perceived by the DRAM. There is no requirement, nor strong need, to have a specific wiring relationship between the address/control logic path and the data path to each DRAM. Hence, the timing relationships between these two interfaces changes at each DRAM and signals on both these interfaces must arrive at each DRAM with the proper timing relationship. There is a common industry methodology to variably delay the memory controller's data path to each DRAM and calibrate this delay structure to assure proper timing relationships at the DRAM. Write leveling is used to indicate such a calibration process that involves a test mode that is entered by commanding the DRAM, via a mode register command, to align the DQS, to the memory reference clock, as seen by the DRAM. This process does not assure that, for normal write commands, the data strobes are on the correct clock cycle. Write leveling assures a basic core timing relationship between a data strobe edge and ‘any given’ clock edge. It does not assure that proper CWL will be maintained.
With increasing operating rates (frequency/speed) of the interfaces, propagation delay can become significant. As propagation delay closes in on, or exceeds the clock period (operating frequency/data rate), the skew between the command interface and data interface can change significantly relative to the memory controller and any particular DRAM device. This is because the address and control logic signals can travel much farther in distance than their companion data interface signals. From the perspective of the memory controller, the write command and data strobe will have the programmed delay that it believes meets the required CWL requirement, however, due to the possibility of increasing skew between the address/control logic and the data bus, at each DRAM, the proper CWL might not be achieved at the DRAM.
Contemporary methodologies for validating CWL are based on a trial and error approach. A write/read cycle is executed by a memory controller to determine if data written, by a write command to a memory address, is returned correctly in response to a read command to the same memory address. Matching return data implies that the write is being performed with the correct CWL. Incorrect return data can imply the need to adjust the CWL, either forward or backward, and then requires re-testing with another write/read cycle. The trial and error approach of the current methodology can cause certain DRAMs to fail, and may require other methods of circumvention (e.g., issue two identical writes to flush the write through). The trial and error approach can be performed using a hardware assist (e.g., a state machine) and/or low level software (e.g., firmware) to perform a write/read compare operation and cycle adjustment until a successful compare is found.
A drawback to contemporary approaches is that it may be difficult to assure proper DRAM behavior when attempting to find the proper write latency with a trail and error approach. Another drawback is the amount of time required during initialization to perform numerous iterations, particularly when using a single service processor to initialize memory systems with large memory arrays.
Accordingly, and while existing memory systems may be suitable for their intended purposes, there remains a need in the art for memory systems that overcome these drawbacks for memory designs that have differences in timing relationships between the memory controller and numerous connected memory devices that operate at high frequency.